In a conventional NAND memory cell arrangement, the memory cells are coupled to the bit lines via respective contact holes that are etched into inter metal dielectric material. The contact holes are filled with poly-silicon.
It is desirable to provide minimum pitch contact holes of a NAND memory cell arrangement. However, in order to achieve this, new and expensive lithography techniques are required with a higher resolution.
For these and other reasons, there is a need for the present invention as set forth in the following embodiments.